1. Field
The following description relates to a memory configuring a computer, and more particularly, to a memory that may temporarily store data based on a calculation of a processor core.
2. Related Art
A cache memory is provided to more efficiently use memory in a computer system. Typically, it is a memory which is located between a processor core and a main memory, operates more quickly than the main memory, and is smaller than the main memory.
Because data accessed by the processor core generally has a good possibility of being accessed again in the near future, the data accessed by the processor core may be stored in the cache memory and may be quickly accessed when an access request occurs again.
For example, when the data requested by the processor core is stored in the cache memory, the processor core may quickly access the data requested from the cache memory instead of the main memory, thereby reducing an operation time.
As another example, when the data requested by the processor core is not stored in the cache memory, the processor core may need to access the data requested from the main memory instead of the cache memory, and a time required for this process may be longer than a time required for accessing the data from the cache memory.
As described above, a case in which the data requested by the processor core is stored in the cache memory denotes that a cache hit occurs, and a case in which the data requested by the processor core is not stored in the cache memory denotes that a cache miss occurs.
A Scratch Pad Memory (SPM) may be used as a memory device that is combined with the processor core and that stores data.
The SPM may exclude an additional circuit for determining either a hit or a miss, different from that of the cache memory, and is controlled by legacy software for correct operation of the SPM.
Selection, configuration, and use of at least one of a cache and the SPM may be different according to a processor architecture.
Accordingly, there is a need for a processor architecture including a cache and a SPM, enabling more efficient operation of the cache and the SPM, and a memory control method.